The present invention relates to semiconductor fabrication, and more specifically, to systems and methods for fabricating a vertical heterojunction tunnel field effect transistor (FET) implementing a planar process.
Tunnel-FETs are proposed as a replacement for/complement to existing CMOS technology. Tunnel-FET structures with a heterojunction on the source side of the device are preferred since they can increase device performance while suppressing parasitic ambipolar behavior at the drain end. Existing tunnel-FET designs predominantly use a tunnel-junction perpendicular to the gate, rather than parallel, which reduces the effectiveness of the gate field. Other designs which use a gate-parallel tunnel path either do not have a heterojunction or have one which also exists on the drain side, increasing parasitic ambipolar current.